The following email has been sent to NOY, Matthew:
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Dear Matthew Noy,
The submission of your abstract has been successfully processed.
Abstract submitted: https://indico.cern.ch/userAbstracts.py?confId=192695.
Status of your abstract: https://indico.cern.ch/abstractDisplay.py?abstractId=104&confId=192695.
See below a detailed summary of your submitted abstract:
Conference: Tipp 2014 - Third International Conference on Technology and Instrumentation in Particle Physics
Submitted by: NOY, Matthew
Submitted on: 30 January 2014 14:11
Title: The TDCPix ASIC: Tracking for the NA62 GigaTracker
Abstract content The TDCPix is a hybrid pixel detector readout ASIC designed for the NA62 GigaTracker detector. The requirements are a single-hit timing resolution better than 200ps RMS, a hit loss of less than 1% in the presence of a (highly non-uniform) beam rate up to 1MHz/cm^2. This hit rate leads to an expected data rate at the output of the chip which can reach 6Gb/s.
The TDCPix comprises an asynchronously operating pixel array of 40 columns of 45 pixels, each 300 microns x 300 microns. This is instrumented with 40 Delay Locked Loop based time-to-digital converters connected to data buffering and concentrating logic. The read-out uses four 3.2Gb/s serialisers with the high speed clock being provided by a low-noise on-chip PLL. The high data rates negate the possibility of buffering whilst awaiting a trigger, thus a self triggering architecture has been adopted.
All configuration and state logic in the design deemed critical for the correct operation of the chip has been triplicated to provide increased single event effect tolerance. A number of on-chip digital-to-analogue converters provide threshold generation and trimming and are configurable through a single-signal configuration interface. The configuration and DAQ interfaces include a DC-balanced protocol layer permitting direct optical connections when the ASIC is installed in the experiment. Dedicated calibration circuitry is included to enable the required timing resolution to be reached.
The chip has been manufactured in a commercial 130nm process and testing is underway. A detailed description of the architecture and performance results will be presented.
Summary
Primary Authors: NOY, Matthew (CERN) matthew.noy@cern.ch
Co-authors: Dr. AGLIERI RINELLA, Gianluca (CERN) gianluca.aglieri.rinella@cern.ch BONACINI, Sandro (CERN) sandro.bonacini@cern.ch KAPLON, Jan (CERN) jan.kaplon@cern.ch KLUGE, Alex (CERN) alexander.kluge@cern.ch MOREL, Michel (CERN) michel.morel@cern.ch PERKTOLD, Lukas (Graz University of Technology (AT)) lukas.perktold@cern.ch POLTORAK, Karolina (AGH University of Science and Technology (PL)) karolina.poltorak@cern.ch
Abstract presenters: NOY, Matthew
Track classification: Sensors: 1b) Semiconductor Detectors Data-processing: 3a) Front-end Electronics
Presentation type: --not specified--
Comments: I would like to give an oral presentation, but the form only allows me to select "not specified."