The following email has been sent to OBERLA, Eric:

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Dear eric oberla,

The submission of your abstract has been successfully processed.

Abstract submitted: https://indico.cern.ch/event/192695/call-for- abstracts/my-abstracts.

Status of your abstract: https://indico.cern.ch/event/192695/call- for-abstracts/394/.

See below a detailed summary of your submitted abstract:

Conference: Tipp 2014 - Third International Conference on Technology and Instrumentation in Particle Physics

Submitted by: OBERLA, Eric

Submitted on: 28 February 2014 21:45

Title: A Data Acquisition System using the 10 GSa/s PSEC4 Waveform Digitizing ASIC

Abstract content A data acquisition (DAQ) system using the 10 Gigasample/second (GSa/s) PSEC4 waveform recording Application Specific Integrated Circuit (ASIC) has been developed as part of the Large Area Picosecond Photo-Detector Collaboration (LAPPD). The LAPPD collaboration is developing 20$\times$20 cm$^2$ glass-body micro-channel plate (MCP) photomultiplier tubes equipped with an economical 1.5 GHz, 30-channel microstrip anode to extract the MCP signals. The PSEC4 chip, a 6-channel 0.13 $\mu$m CMOS waveform digitizer, was designed by the Universities of Chicago and Hawai'i as a first generation readout ASIC for these photosensors [1]. A PSEC4-based DAQ system that is capable of reading out a number of LAPPD MCPs was subsequently developed by our group. The system architecture incorporates two levels of hardware, FPGA-embedded system control, and data processing. At the front-end is a 30 channel unit that holds five PSEC4 ASICs and a control FPGA that plugs directly into one terminal of the LAPPD MCP anode. The analog bandwidth of the signal input is 1.5 GHz. In order to record waveforms at both ends of the LAPPD anode, two of these cards are required to fully instrument an LAPPD MCP. The back-end card houses the system control FPGA, distributes the system clock, and manages up to four front-end units by means of eight 800 Mbps LVDS lines. This back-end card communicates to a PC using USB 2.0 or gigabit Ethernet. The system performance and LAPPD detector-integrated testing results will be presented.

[1] NIM A732, p452, Jan 2014.

Summary

Primary Authors: OBERLA, Eric (uchicago) ejo@uchicago.edu

Co-authors: FRISCH, Henry (u) frisch@hep.uchicago.edu VARNER, Gary (University of Hawaii) varner@phys.hawaii.edu BOGDAN, Mircea (The University of Chicago) bogdan@edg.uchicago.edu

Abstract presenters: OBERLA, Eric

Track classification: Data-processing: 3b) Trigger and Data Acquisition Systems

Presentation type: Poster

Comments: